Delayed precise invalidation - A software cache coherence scheme

T. S. Hwang*, N. P. Lu, Chung-Ping Chung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named 'delayed precise invalidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, this scheme provides more cacheability and allows invalidation of partial elements in an array, overcoming some inefficiencies and deficiencies of previous software cache coherence schemes.

Original languageEnglish
Pages (from-to)337-344
Number of pages8
JournalIEE Proceedings: Computers and Digital Techniques
Volume143
Issue number5
DOIs
StatePublished - Sep 1996

Keywords

  • Cache coherence
  • Compilers
  • Invalidation

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