Delay-difference DLL and its-application on skewed output buffer

Ya Lan Tsao; Ming Chao Chung; Shyh-Jye Jou

doi:10.1109/APASIC.2002.1031586

Delay-difference DLL and its-application on skewed output buffer

Ya Lan Tsao, Ming Chao Chung, Shyh-Jye Jou

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	279-282
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031586
State	Published - 1 Jan 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan Duration: 6 Aug 2002 → 8 Aug 2002

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan
City	Taipei
Period	6/08/02 → 8/08/02

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10.1109/APASIC.2002.1031586

Cite this

Tsao, Y. L., Chung, M. C., & Jou, S-J. (2002). Delay-difference DLL and its-application on skewed output buffer. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 279-282). Article 1031586 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031586

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abstract = "The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.",

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Tsao, YL, Chung, MC & Jou, S-J 2002, Delay-difference DLL and its-application on skewed output buffer. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031586, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 279-282, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, 6/08/02. https://doi.org/10.1109/APASIC.2002.1031586

Delay-difference DLL and its-application on skewed output buffer. / Tsao, Ya Lan; Chung, Ming Chao; Jou, Shyh-Jye.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 279-282 1031586 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Delay-difference DLL and its-application on skewed output buffer

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