Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators

Ning Chi Huang*, Min Syue Yang, Ya Chu Chang, Kai Chiang Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As the demand for data analysis increases rapidly, artificial intelligence (AI) models have been developed for various applications. Many deep neural networks are presented with millions or billions of parameters and operations for AI computation. Therefore, many AI accelerators apply pipelined architectures with simple but dense computational elements for numerous operations. However, manufacturing-induced faults cause a challenge to computational robustness or yield degradation on those AI accelerators. In this paper, we propose a fault mitigation methodology based on decomposable systolic arrays. By leveraging the inherent error resilience of AI applications, our data arrangement can reduce the difference between accurate results and faulty results. Additionally, utilizing both our proposed data arrangement and sign compensation can further mitigate the influence of faults in AI accelerators. In the experiments, our proposed fault mitigation methodology can maintain the application accuracy at a certain level, which outperforms state-of-the-art methods. When 0.1% of multiplier-accumulators are faulty in a systolic array, the array with our proposed fault mitigation methodology can have less than 0.5% accuracy loss while executing ResNet-18 for ImageNet classification.

Original languageEnglish
Title of host publicationProceedings of the 24th International Symposium on Quality Electronic Design, ISQED 2023
PublisherIEEE Computer Society
ISBN (Electronic)9798350334753
DOIs
StatePublished - 2023
Event24th International Symposium on Quality Electronic Design, ISQED 2023 - San Francisco, United States
Duration: 5 Apr 20237 Apr 2023

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2023-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference24th International Symposium on Quality Electronic Design, ISQED 2023
Country/TerritoryUnited States
CitySan Francisco
Period5/04/237/04/23

Keywords

  • data arrangement
  • decomposable systolic array
  • deep learning accelerator
  • fault mitigation
  • sign compensation

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