DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the scalability of CTFET under critical dimensions (n- to p-TFET separation, nanosheet pitch, and so on), and find that it is highly scalable. The circuit analysis of CTFET-inverter show high-noise margin (NM) and voltage gains compared to the conventional strained-Si GAA-TFETs at the supply range (V _DD) from 0.7 ≥ V _DD ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. Improved circuit performance, followed by 12.5% and 21.5% improvements in low and high NMs (NM_L and NM_H) are seen in CTFETs compared to conventional TFETs.