Data compression and VLSI implementation neuroprocessor

W. C. Fang

doi:10.1109/ASIC.1993.410846

Data compression and VLSI implementation neuroprocessor

W. C. Fang^*

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

VLSI data compression research has been motivated by the needs of high-speed high-performance data compression and inspired by the VLSI technologies. An integrated data compression system has been proposed to provide adaptive multi-mode data compression for an advanced multi-instrument spacecraft payload system that has various source data. It combines a high-ratio lossy data compressor with a lossless data compressor to provide various compression schemes. The embedded lossy compressor is a high-speed neuroprocessor for adaptive vector quantization based upon a frequency-sensitive self-organization neural algorithm. The embedded lossless compressor is a high-speed pipelined processor design based on the Rice algorithm.

Original language	English
Title of host publication	Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	570-579
Number of pages	10
ISBN (Electronic)	0780313755, 9780780313750
DOIs	https://doi.org/10.1109/ASIC.1993.410846
State	Published - 1993
Event	6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993 - Rochester, United States Duration: 27 Sep 1993 → 1 Oct 1993

Publication series

Name	Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993

Conference

Conference	6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993
Country/Territory	United States
City	Rochester
Period	27/09/93 → 1/10/93

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10.1109/ASIC.1993.410846

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Fang, W. C. (1993). Data compression and VLSI implementation neuroprocessor. In Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993 (pp. 570-579). Article 410846 (Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1993.410846

@inproceedings{e5cd59146cba4ce396df897ab6798699,

title = "Data compression and VLSI implementation neuroprocessor",

abstract = "VLSI data compression research has been motivated by the needs of high-speed high-performance data compression and inspired by the VLSI technologies. An integrated data compression system has been proposed to provide adaptive multi-mode data compression for an advanced multi-instrument spacecraft payload system that has various source data. It combines a high-ratio lossy data compressor with a lossless data compressor to provide various compression schemes. The embedded lossy compressor is a high-speed neuroprocessor for adaptive vector quantization based upon a frequency-sensitive self-organization neural algorithm. The embedded lossless compressor is a high-speed pipelined processor design based on the Rice algorithm.",

author = "Fang, {W. C.}",

note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993 ; Conference date: 27-09-1993 Through 01-10-1993",

year = "1993",

doi = "10.1109/ASIC.1993.410846",

language = "English",

series = "Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "570--579",

booktitle = "Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993",

address = "美國",

}

Fang, WC 1993, Data compression and VLSI implementation neuroprocessor. in Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993., 410846, Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993, Institute of Electrical and Electronics Engineers Inc., pp. 570-579, 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993, Rochester, United States, 27/09/93. https://doi.org/10.1109/ASIC.1993.410846

Data compression and VLSI implementation neuroprocessor. / Fang, W. C.
Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993. Institute of Electrical and Electronics Engineers Inc., 1993. p. 570-579 410846 (Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - VLSI data compression research has been motivated by the needs of high-speed high-performance data compression and inspired by the VLSI technologies. An integrated data compression system has been proposed to provide adaptive multi-mode data compression for an advanced multi-instrument spacecraft payload system that has various source data. It combines a high-ratio lossy data compressor with a lossless data compressor to provide various compression schemes. The embedded lossy compressor is a high-speed neuroprocessor for adaptive vector quantization based upon a frequency-sensitive self-organization neural algorithm. The embedded lossless compressor is a high-speed pipelined processor design based on the Rice algorithm.

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BT - Proceedings - 6th Annual IEEE International ASIC Conference and Exhibit, ASIC 1993

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Y2 - 27 September 1993 through 1 October 1993

ER -

Data compression and VLSI implementation neuroprocessor

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