TY - JOUR
T1 - Cryogenic Embedded System to Support Quantum Computing
T2 - From 5-nm FinFET to Full Processor
AU - Genssler, Paul R.
AU - Klemme, Florian
AU - Parihar, Shivendra Singh
AU - Brandhofer, Sebastian
AU - Pahwa, Girish
AU - Polian, Ilia
AU - Chauhan, Yogesh Singh
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2023
Y1 - 2023
N2 - Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature (300). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-The-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-The-Art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and 300. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at 300 and analyze its performance at 10. Our simulations show that the SoC at 10 is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.
AB - Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more quantum bits (qubits). One obstacle for scaling up quantum computers is the connection between their cryogenic qubits at temperatures between a few millikelvin and a few kelvin (depending on qubit type) and the classical processing system on chip (SoC) at room temperature (300). Through this connection, outside heat leaks to the qubits and can disrupt their state. Hence, moving the SoC into the cryogenic part eliminates this heat leakage. However, the cooling capacity is limited, requiring a low-power SoC, which, at the same time, has to classify qubit measurements under a tight time constraint. In this work, we explore for the first time if an off-The-shelf SoC is a plausible option for such a task. Our analysis starts with measurements of state-of-The-Art 5-nm fin-shaped field-effect transistors (FinFETs) at 10 and 300. Then, we calibrate a transistor compact model and create two standard cell libraries, one for each temperature. We perform synthesis and physical layout of a RISC-V SoC at 300 and analyze its performance at 10. Our simulations show that the SoC at 10 is plausible but lacks the performance to process more than a few thousand qubits under the time constraint.
KW - 5-nm fin-shaped field-effect transistor (FinFET)
KW - Cryogenic CMOS
KW - hyperdimensional computing
KW - machine learning classification
KW - quantum computing
KW - system on chip (SoC)
UR - http://www.scopus.com/inward/record.url?scp=85166782364&partnerID=8YFLogxK
U2 - 10.1109/TQE.2023.3300833
DO - 10.1109/TQE.2023.3300833
M3 - Article
AN - SCOPUS:85166782364
SN - 2689-1808
VL - 4
JO - IEEE Transactions on Quantum Engineering
JF - IEEE Transactions on Quantum Engineering
M1 - 5500611
ER -