Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs

Shivendra Singh Parihar; Girish Pahwa; Jun Z. Huang; Weike Wang; Kimihiko Imura; Chenming Hu; Yogesh Singh Chauhan

doi:10.1109/EDTM55494.2023.10102942

Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs

Shivendra Singh Parihar, Girish Pahwa, Jun Z. Huang, Weike Wang, Kimihiko Imura, Chenming Hu, Yogesh Singh Chauhan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

We present cryogenic characterization and compact model extraction of commercially fabricated 5nm technology FinFETs. A modified industry-standard BSIM-CMG model is used to accurately model band-tail, mobility, and velocity saturation effects up to 10K. At 10K, n-FinFET and p-FinFET show 87mV and 92mV threshold voltage shift and sub-threshold slopes of 12.7 and 16.7mV/decade (83% and 78% improvement), respectively. The simulated inverter and ring oscillator at 10K in iso IOFF condition show 38% and 36.53% delay improvement for VDD = 0.75V, respectively. At VDD = 0.35V, inverter simulations show ∼ 70% improvement in delay and Power-Delay-Product. Static leakage and power dissipation are major challenges in FinFETs; the above-mentioned performance enhancements highlight the potential of characterized technology in quantum computers.

Original language	English
Title of host publication	7th IEEE Electron Devices Technology and Manufacturing Conference
Subtitle of host publication	Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350332520
DOIs	https://doi.org/10.1109/EDTM55494.2023.10102942
State	Published - 2023
Event	7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023 - Seoul, Korea, Republic of Duration: 7 Mar 2023 → 10 Mar 2023

Publication series

Name	7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023

Conference

Conference	7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023
Country/Territory	Korea, Republic of
City	Seoul
Period	7/03/23 → 10/03/23

Keywords

5nm FinFET
Characterization
Cryogenic
Modeling
Quantum Computing)

Access to Document

10.1109/EDTM55494.2023.10102942

Cite this

Parihar, S. S., Pahwa, G., Huang, J. Z., Wang, W., Imura, K., Hu, C., & Chauhan, Y. S. (2023). Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs. In 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023 (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM55494.2023.10102942

Parihar, Shivendra Singh ; Pahwa, Girish ; Huang, Jun Z. et al. / Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs. 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023).

@inproceedings{117c42bd34164b1ead22a20c6dae598e,

title = "Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs",

abstract = "We present cryogenic characterization and compact model extraction of commercially fabricated 5nm technology FinFETs. A modified industry-standard BSIM-CMG model is used to accurately model band-tail, mobility, and velocity saturation effects up to 10K. At 10K, n-FinFET and p-FinFET show 87mV and 92mV threshold voltage shift and sub-threshold slopes of 12.7 and 16.7mV/decade (83\% and 78\% improvement), respectively. The simulated inverter and ring oscillator at 10K in iso IOFF condition show 38\% and 36.53\% delay improvement for VDD = 0.75V, respectively. At VDD = 0.35V, inverter simulations show ∼ 70\% improvement in delay and Power-Delay-Product. Static leakage and power dissipation are major challenges in FinFETs; the above-mentioned performance enhancements highlight the potential of characterized technology in quantum computers.",

keywords = "5nm FinFET, Characterization, Cryogenic, Modeling, Quantum Computing)",

author = "Parihar, \{Shivendra Singh\} and Girish Pahwa and Huang, \{Jun Z.\} and Weike Wang and Kimihiko Imura and Chenming Hu and Chauhan, \{Yogesh Singh\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023 ; Conference date: 07-03-2023 Through 10-03-2023",

year = "2023",

doi = "10.1109/EDTM55494.2023.10102942",

language = "English",

series = "7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "7th IEEE Electron Devices Technology and Manufacturing Conference",

address = "美國",

}

Parihar, SS, Pahwa, G, Huang, JZ, Wang, W, Imura, K, Hu, C & Chauhan, YS 2023, Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs. in 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023, Institute of Electrical and Electronics Engineers Inc., 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023, Seoul, Korea, Republic of, 7/03/23. https://doi.org/10.1109/EDTM55494.2023.10102942

Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs. / Parihar, Shivendra Singh; Pahwa, Girish; Huang, Jun Z. et al.
7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs

AU - Parihar, Shivendra Singh

AU - Pahwa, Girish

AU - Huang, Jun Z.

AU - Wang, Weike

AU - Imura, Kimihiko

AU - Hu, Chenming

AU - Chauhan, Yogesh Singh

PY - 2023

Y1 - 2023

N2 - We present cryogenic characterization and compact model extraction of commercially fabricated 5nm technology FinFETs. A modified industry-standard BSIM-CMG model is used to accurately model band-tail, mobility, and velocity saturation effects up to 10K. At 10K, n-FinFET and p-FinFET show 87mV and 92mV threshold voltage shift and sub-threshold slopes of 12.7 and 16.7mV/decade (83% and 78% improvement), respectively. The simulated inverter and ring oscillator at 10K in iso IOFF condition show 38% and 36.53% delay improvement for VDD = 0.75V, respectively. At VDD = 0.35V, inverter simulations show ∼ 70% improvement in delay and Power-Delay-Product. Static leakage and power dissipation are major challenges in FinFETs; the above-mentioned performance enhancements highlight the potential of characterized technology in quantum computers.

AB - We present cryogenic characterization and compact model extraction of commercially fabricated 5nm technology FinFETs. A modified industry-standard BSIM-CMG model is used to accurately model band-tail, mobility, and velocity saturation effects up to 10K. At 10K, n-FinFET and p-FinFET show 87mV and 92mV threshold voltage shift and sub-threshold slopes of 12.7 and 16.7mV/decade (83% and 78% improvement), respectively. The simulated inverter and ring oscillator at 10K in iso IOFF condition show 38% and 36.53% delay improvement for VDD = 0.75V, respectively. At VDD = 0.35V, inverter simulations show ∼ 70% improvement in delay and Power-Delay-Product. Static leakage and power dissipation are major challenges in FinFETs; the above-mentioned performance enhancements highlight the potential of characterized technology in quantum computers.

KW - 5nm FinFET

KW - Characterization

KW - Cryogenic

KW - Modeling

KW - Quantum Computing)

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U2 - 10.1109/EDTM55494.2023.10102942

DO - 10.1109/EDTM55494.2023.10102942

M3 - Conference contribution

AN - SCOPUS:85158164540

T3 - 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023

BT - 7th IEEE Electron Devices Technology and Manufacturing Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023

Y2 - 7 March 2023 through 10 March 2023

ER -

Parihar SS, Pahwa G, Huang JZ, Wang W, Imura K, Hu C et al. Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs. In 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023). doi: 10.1109/EDTM55494.2023.10102942

Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs

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Keywords

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