TY - GEN
T1 - Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches
AU - Chen, Ying Liang
AU - Hsu, Terng Yin
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/2/2
Y1 - 2015/2/2
N2 - In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.
AB - In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.
KW - Dynamic Current Scaling (DCS)
KW - Fast Fourier Transform (FFT)
KW - Pipelined-based Architecture
UR - http://www.scopus.com/inward/record.url?scp=84924285518&partnerID=8YFLogxK
U2 - 10.1109/ISICIR.2014.7029577
DO - 10.1109/ISICIR.2014.7029577
M3 - Conference contribution
AN - SCOPUS:84924285518
T3 - Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
SP - 184
EP - 187
BT - Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International Symposium on Integrated Circuits, ISIC 2014
Y2 - 10 December 2014 through 12 December 2014
ER -