TY - GEN
T1 - Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-To-source/drain underlap
AU - Hu, Vita Pi Ho
AU - Lo, Chang Ting
AU - Sachid, Angada B.
AU - Su, Pin
AU - Hu, Chen-Ming
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/27
Y1 - 2016/5/27
N2 - Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-To-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-To-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.
AB - Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-To-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-To-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.
UR - http://www.scopus.com/inward/record.url?scp=84978698293&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2016.7480515
DO - 10.1109/VLSI-TSA.2016.7480515
M3 - Conference contribution
AN - SCOPUS:84978698293
T3 - 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
BT - 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
Y2 - 25 April 2016 through 27 April 2016
ER -