Compute-in-Time for Deep Neural Network Accelerators: Challenges and Prospects

Hamza Al Maharmeh, Nabil J. Sarhan, Chung Chih Hung, Mohammed Ismail, Mohammad Alhawari

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Time-domain (TD) accelerators leverage both digital and analog features, thereby enabling energy-efficient computing and scaling with CMOS technology. This paper reviews state-of-the-art TD accelerators and discusses system considerations and hardware implementations, including the spatially unrolled and recursive TD architectures. Additionally, the paper analyzes the energy and area efficiency of the TD architectures for varying input resolutions and network sizes. This analysis provides insight for designers into how to choose the appropriate TD approach for a particular application.

Original languageEnglish
Title of host publication2020 IEEE 63rd International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages990-993
Number of pages4
ISBN (Electronic)9781538629161
DOIs
StatePublished - Aug 2020
Event63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020 - Springfield, United States
Duration: 9 Aug 202012 Aug 2020

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2020-August
ISSN (Print)1548-3746

Conference

Conference63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020
Country/TerritoryUnited States
CitySpringfield
Period9/08/2012/08/20

Keywords

  • Analog Domain
  • Recursive
  • Spatially Unrolled
  • Time-Domain (TD) Accelerators
  • Time-Domain Computation

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