Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

Ming-Dou Ker; Kuo Chun Hsu

doi:10.1109/ASIC.2002.1158061

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

Ming-Dou Ker, Kuo Chun Hsu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices, which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-μm STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.

Original language	English
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	229-233
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158061
State	Published - 2002
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: 25 Sep 2002 → 28 Sep 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Conference

Conference	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	25/09/02 → 28/09/02

Access to Document

10.1109/ASIC.2002.1158061

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Ker, M.-D., & Hsu, K. C. (2002). Complementary substrate-triggered SCR devices for on-chip ESD protection circuits. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 229-233). Article 1158061 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158061

Ker, Ming-Dou ; Hsu, Kuo Chun. / Complementary substrate-triggered SCR devices for on-chip ESD protection circuits. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 229-233 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

@inproceedings{7ed5da2b39574d39b8ecb690a9c2d084,

title = "Complementary substrate-triggered SCR devices for on-chip ESD protection circuits",

abstract = "The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices, which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-μm STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.",

author = "Ming-Dou Ker and Hsu, {Kuo Chun}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 ; Conference date: 25-09-2002 Through 28-09-2002",

year = "2002",

doi = "10.1109/ASIC.2002.1158061",

language = "English",

series = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "229--233",

editor = "John Chickanosky and Krishnamurthy, {Ram K.} and P.R. Mukund",

booktitle = "Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002",

address = "美國",

}

Ker, M-D & Hsu, KC 2002, Complementary substrate-triggered SCR devices for on-chip ESD protection circuits. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158061, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 229-233, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 25/09/02. https://doi.org/10.1109/ASIC.2002.1158061

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits. / Ker, Ming-Dou; Hsu, Kuo Chun.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 229-233 1158061 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

AU - Ker, Ming-Dou

AU - Hsu, Kuo Chun

PY - 2002

Y1 - 2002

N2 - The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices, which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-μm STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.

AB - The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices, which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-μm STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.

UR - http://www.scopus.com/inward/record.url?scp=79956346072&partnerID=8YFLogxK

U2 - 10.1109/ASIC.2002.1158061

DO - 10.1109/ASIC.2002.1158061

M3 - Conference contribution

AN - SCOPUS:79956346072

T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SP - 229

EP - 233

BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

A2 - Chickanosky, John

A2 - Krishnamurthy, Ram K.

A2 - Mukund, P.R.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

Y2 - 25 September 2002 through 28 September 2002

ER -

Ker MD, Hsu KC. Complementary substrate-triggered SCR devices for on-chip ESD protection circuits. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 229-233. 1158061. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158061

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

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