Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Tao Cheng; Tain Shun Wu

doi:10.1109/ISCAS.1995.519892

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Tao Cheng, Tain Shun Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

12 Scopus citations

Abstract

There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

Original language	English
Article number	5099908
Pages (from-to)	833-836
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.1995.519892
State	Published - 1 Jan 1995
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 30 Apr 1995 → 3 May 1995

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10.1109/ISCAS.1995.519892

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title = "Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's",

abstract = "There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Tao Cheng and Wu, {Tain Shun}",

year = "1995",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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T1 - Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Cheng, Tao

AU - Wu, Tain Shun

PY - 1995/1/1

Y1 - 1995/1/1

N2 - There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

AB - There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

UR - http://www.scopus.com/inward/record.url?scp=0029204489&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1995.519892

DO - 10.1109/ISCAS.1995.519892

M3 - Conference article

AN - SCOPUS:0029204489

SN - 0271-4310

VL - 2

SP - 833

EP - 836

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 5099908

Y2 - 30 April 1995 through 3 May 1995

ER -

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

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