Compiler supports and optimizations for PAC VLIW DSP processors

Yung Chia Lin; Chung Lin Tang; Chung Ju Wu; Ming Yu Hung; Yi-Ping You; Ya Chiao Moo; Sheng Yuan Chen; Jenq Kuen Lee

doi:10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors

Yung Chia Lin^*, Chung Lin Tang, Chung Ju Wu, Ming Yu Hung, Yi-Ping You, Ya Chiao Moo, Sheng Yuan Chen, Jenq Kuen Lee

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

Original language	English
Title of host publication	Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers
Pages	466-474
Number of pages	9
DOIs	https://doi.org/10.1007/978-3-540-69330-7_34
State	Published - 2006
Event	18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 - Hawthorne, NY, United States Duration: 20 Oct 2005 → 22 Oct 2005

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4339 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
Country/Territory	United States
City	Hawthorne, NY
Period	20/10/05 → 22/10/05

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10.1007/978-3-540-69330-7_34

Cite this

Lin, Y. C., Tang, C. L., Wu, C. J., Hung, M. Y., You, Y.-P., Moo, Y. C., Chen, S. Y., & Lee, J. K. (2006). Compiler supports and optimizations for PAC VLIW DSP processors. In Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers (pp. 466-474). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4339 LNCS). https://doi.org/10.1007/978-3-540-69330-7_34

Lin, Yung Chia ; Tang, Chung Lin ; Wu, Chung Ju et al. / Compiler supports and optimizations for PAC VLIW DSP processors. Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. pp. 466-474 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{819e17d6dea54ff99ad6b41b0e28b5ab,

title = "Compiler supports and optimizations for PAC VLIW DSP processors",

abstract = "PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.",

author = "Lin, {Yung Chia} and Tang, {Chung Lin} and Wu, {Chung Ju} and Hung, {Ming Yu} and Yi-Ping You and Moo, {Ya Chiao} and Chen, {Sheng Yuan} and Lee, {Jenq Kuen}",

year = "2006",

doi = "10.1007/978-3-540-69330-7_34",

language = "English",

isbn = "3540693297",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "466--474",

booktitle = "Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers",

note = "18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 ; Conference date: 20-10-2005 Through 22-10-2005",

}

Lin, YC, Tang, CL, Wu, CJ, Hung, MY, You, Y-P, Moo, YC, Chen, SY & Lee, JK 2006, Compiler supports and optimizations for PAC VLIW DSP processors. in Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4339 LNCS, pp. 466-474, 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005, Hawthorne, NY, United States, 20/10/05. https://doi.org/10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors. / Lin, Yung Chia; Tang, Chung Lin; Wu, Chung Ju et al.
Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. p. 466-474 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4339 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compiler supports and optimizations for PAC VLIW DSP processors

AU - Lin, Yung Chia

AU - Tang, Chung Lin

AU - Wu, Chung Ju

AU - Hung, Ming Yu

AU - You, Yi-Ping

AU - Moo, Ya Chiao

AU - Chen, Sheng Yuan

AU - Lee, Jenq Kuen

PY - 2006

Y1 - 2006

N2 - PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

AB - PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

UR - http://www.scopus.com/inward/record.url?scp=43949138596&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-69330-7_34

DO - 10.1007/978-3-540-69330-7_34

M3 - Conference contribution

AN - SCOPUS:43949138596

SN - 3540693297

SN - 9783540693291

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 466

EP - 474

BT - Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers

T2 - 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005

Y2 - 20 October 2005 through 22 October 2005

ER -

Lin YC, Tang CL, Wu CJ, Hung MY, You YP, Moo YC et al. Compiler supports and optimizations for PAC VLIW DSP processors. In Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. p. 466-474. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors

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