Compiler supports and optimizations for PAC VLIW DSP processors

Yung Chia Lin*, Chung Lin Tang, Chung Ju Wu, Ming Yu Hung, Yi-Ping You, Ya Chiao Moo, Sheng Yuan Chen, Jenq Kuen Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations


PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

Original languageEnglish
Title of host publicationLanguages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers
Number of pages9
StatePublished - 1 Dec 2006
Event18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 - Hawthorne, NY, United States
Duration: 20 Oct 200522 Oct 2005

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4339 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
Country/TerritoryUnited States
CityHawthorne, NY


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