Compiler optimization on instruction scheduling for low power

Chingren Lee; Jenq Kuen Lee; Ting Ting Hwang; Shi-Chun Tsai

doi:10.1109/ISSS.2000.874029

Compiler optimization on instruction scheduling for low power

Chingren Lee, Jenq Kuen Lee^*, Ting Ting Hwang, Shi-Chun Tsai

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

54 Scopus citations

Abstract

We investigate compiler transformation techniques for the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case we prove that the problem is NP-hard and propose a heuristic algorithm. Experimental results show average 13% improvements with the 4-way issue architecture and average 20% improvement with the 8-way issue architecture for power consumption of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.

Original language	English
Title of host publication	Proceedings - 13th International Symposium on System Synthesis, ISSS 2000
Publisher	IEEE Computer Society
Pages	55-60
Number of pages	6
ISBN (Electronic)	0769507654
DOIs	https://doi.org/10.1109/ISSS.2000.874029
State	Published - 2000
Event	13th International Symposium on System Synthesis, ISSS 2000 - Madrid, Spain Duration: 20 Sep 2000 → 22 Sep 2000

Publication series

Name	Proceedings of the International Symposium on System Synthesis
Volume	2000-January
ISSN (Print)	1080-1820

Conference

Conference	13th International Symposium on System Synthesis, ISSS 2000
Country/Territory	Spain
City	Madrid
Period	20/09/00 → 22/09/00

Keywords

Capacitance
Circuits
Computer architecture
Costs
Energy consumption
Greedy algorithms
Optimizing compilers
Processor scheduling
Software performance
VLIW

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISSS.2000.874029

Cite this

Lee, C., Lee, J. K., Hwang, T. T., & Tsai, S.-C. (2000). Compiler optimization on instruction scheduling for low power. In Proceedings - 13th International Symposium on System Synthesis, ISSS 2000 (pp. 55-60). Article 874029 (Proceedings of the International Symposium on System Synthesis; Vol. 2000-January). IEEE Computer Society. https://doi.org/10.1109/ISSS.2000.874029

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title = "Compiler optimization on instruction scheduling for low power",

abstract = "We investigate compiler transformation techniques for the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case we prove that the problem is NP-hard and propose a heuristic algorithm. Experimental results show average 13% improvements with the 4-way issue architecture and average 20% improvement with the 8-way issue architecture for power consumption of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.",

keywords = "Capacitance, Circuits, Computer architecture, Costs, Energy consumption, Greedy algorithms, Optimizing compilers, Processor scheduling, Software performance, VLIW",

author = "Chingren Lee and Lee, {Jenq Kuen} and Hwang, {Ting Ting} and Shi-Chun Tsai",

note = "Publisher Copyright: {\textcopyright} 2000 IEEE.; 13th International Symposium on System Synthesis, ISSS 2000 ; Conference date: 20-09-2000 Through 22-09-2000",

year = "2000",

doi = "10.1109/ISSS.2000.874029",

language = "English",

series = "Proceedings of the International Symposium on System Synthesis",

publisher = "IEEE Computer Society",

pages = "55--60",

booktitle = "Proceedings - 13th International Symposium on System Synthesis, ISSS 2000",

address = "United States",

}

Lee, C, Lee, JK, Hwang, TT & Tsai, S-C 2000, Compiler optimization on instruction scheduling for low power. in Proceedings - 13th International Symposium on System Synthesis, ISSS 2000., 874029, Proceedings of the International Symposium on System Synthesis, vol. 2000-January, IEEE Computer Society, pp. 55-60, 13th International Symposium on System Synthesis, ISSS 2000, Madrid, Spain, 20/09/00. https://doi.org/10.1109/ISSS.2000.874029

Compiler optimization on instruction scheduling for low power. / Lee, Chingren; Lee, Jenq Kuen; Hwang, Ting Ting et al.
Proceedings - 13th International Symposium on System Synthesis, ISSS 2000. IEEE Computer Society, 2000. p. 55-60 874029 (Proceedings of the International Symposium on System Synthesis; Vol. 2000-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Compiler optimization on instruction scheduling for low power

AU - Lee, Chingren

AU - Lee, Jenq Kuen

AU - Hwang, Ting Ting

AU - Tsai, Shi-Chun

PY - 2000

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N2 - We investigate compiler transformation techniques for the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case we prove that the problem is NP-hard and propose a heuristic algorithm. Experimental results show average 13% improvements with the 4-way issue architecture and average 20% improvement with the 8-way issue architecture for power consumption of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.

AB - We investigate compiler transformation techniques for the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case we prove that the problem is NP-hard and propose a heuristic algorithm. Experimental results show average 13% improvements with the 4-way issue architecture and average 20% improvement with the 8-way issue architecture for power consumption of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.

KW - Capacitance

KW - Circuits

KW - Computer architecture

KW - Costs

KW - Energy consumption

KW - Greedy algorithms

KW - Optimizing compilers

KW - Processor scheduling

KW - Software performance

KW - VLIW

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M3 - Conference contribution

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BT - Proceedings - 13th International Symposium on System Synthesis, ISSS 2000

PB - IEEE Computer Society

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ER -

Compiler optimization on instruction scheduling for low power

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Keywords

UN SDGs

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