Compiler analysis and supports for leakage power reduction on microprocessors

Yi-Ping You*, Chingren Lee, Jenq Kuen Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations


Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts also indicate architecture, compiler, and software participations can help reduce the switching activities (also known as dynamic power) on microprocessors. This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors. In this paper, we investigate the compiler analysis techniques related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating in the component levels. Our compiler gives an analysis framework to utilize the instruction to reduce the leakage power. We present a data flow analysis framework to estimate the component activities at fixed points of programs with the consideration of pipelines of architectures. We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions. As the duration of power gating on components on given program routines is related to program branches, we propose a set of scheduling policy include Basic_Blk_Sched, MIN_Path_Sched, and AVG_Path_Sched mechanisms and evaluate the effectiveness of those schemes. Our experiment is done by incorporating our compiler analysis and scheduling policy into SUIF compiler tools [32] and by simulating the energy consumptions on Wattch toolkits [6]. Experimental results show our mechanisms are effective in reducing leakage powers on microprocessors.

Original languageEnglish
Title of host publicationLanguages and Compilers for Parallel Computing - 15th Workshop, LCPC 2002, Revised Papers
Number of pages16
StatePublished - 1 Dec 2005
Event15th Workshop on Languages and Compilers for Parallel Computing, LCPC 2002 - College Park, MD, United States
Duration: 25 Jul 200227 Jul 2002

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2481 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference15th Workshop on Languages and Compilers for Parallel Computing, LCPC 2002
Country/TerritoryUnited States
CityCollege Park, MD


Dive into the research topics of 'Compiler analysis and supports for leakage power reduction on microprocessors'. Together they form a unique fingerprint.

Cite this