Compilation for compact power-gating controls

Yi-Ping You, Chung Wen Huang, Jenq Kuen Lee*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.

Original languageEnglish
Article number51
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
StatePublished - 1 Sep 2007


  • Balanced scheduling
  • Compilers for low power
  • Data-flow analysis
  • Leakage-power reduction
  • Power-gating mechanisms


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