Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits

Hui Wen Tsai, Ming-Dou Ker

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-μm BCD process to improve latchup immunity.

    Original languageEnglish
    Title of host publication2015 European Conference on Circuit Theory and Design, ECCTD 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781479998777
    DOIs
    StatePublished - 16 Oct 2015
    EventEuropean Conference on Circuit Theory and Design, ECCTD 2015 - Trondheim, Norway
    Duration: 24 Aug 201526 Aug 2015

    Publication series

    Name2015 European Conference on Circuit Theory and Design, ECCTD 2015

    Conference

    ConferenceEuropean Conference on Circuit Theory and Design, ECCTD 2015
    Country/TerritoryNorway
    CityTrondheim
    Period24/08/1526/08/15

    Keywords

    • Latchup
    • electrostatic discharge (ESD) protection
    • guard ring

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