@inproceedings{b6863247438e4f91a8f4ffdc74dc8140,
title = "Comparison of electrical characteristics of N-type silicon junctionless transistors with and without film profile engineering by TCAD simulation",
abstract = "Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (> 1019 cm3) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].",
keywords = "Doping, Logic gates, Performance evaluation, Resistance, Silicon, Thin film transistors",
author = "Tsai, {Jung Ruey} and Horng-Chih Lin and Chang, {Hsiu Fu} and Shie, {Bo Shiuan} and Wen, {Ting Ting} and Huang, {Tiao Yuan}",
note = "Publisher Copyright: {\textcopyright} 2015 JSAP.; Silicon Nanoelectronics Workshop, SNW 2015 ; Conference date: 14-06-2015 Through 15-06-2015",
year = "2015",
month = sep,
day = "24",
language = "American English",
series = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
address = "United States",
}