Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process

Ming-Dou Ker; Wen Yu Lo; Tung Yang Chen; Howard Tang; S. S. Chen; M. C. Wang

doi:10.1109/ISQED.2001.915241

Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process

Ming-Dou Ker, Wen Yu Lo, Tung Yang Chen, Howard Tang, S. S. Chen, M. C. Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-μim shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.

Original language	English
Title of host publication	Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
Publisher	IEEE Computer Society
Pages	267-272
Number of pages	6
ISBN (Electronic)	0769510256
DOIs	https://doi.org/10.1109/ISQED.2001.915241
State	Published - 28 Mar 2001
Event	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States Duration: 26 Mar 2001 → 28 Mar 2001

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2001-January
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
Country/Territory	United States
City	San Jose
Period	26/03/01 → 28/03/01

Access to Document

10.1109/ISQED.2001.915241

Cite this

Ker, M.-D., Lo, W. Y., Chen, T. Y., Tang, H., Chen, S. S., & Wang, M. C. (2001). Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001 (pp. 267-272). Article 915241 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January). IEEE Computer Society. https://doi.org/10.1109/ISQED.2001.915241

Ker, Ming-Dou ; Lo, Wen Yu ; Chen, Tung Yang et al. / Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process. Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, 2001. pp. 267-272 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

@inproceedings{49becb52b6604cd0bdc532a62aaf95a2,

title = "Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process",

abstract = "An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-μim shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.",

author = "Ming-Dou Ker and Lo, {Wen Yu} and Chen, {Tung Yang} and Howard Tang and Chen, {S. S.} and Wang, {M. C.}",

year = "2001",

month = mar,

day = "28",

doi = "10.1109/ISQED.2001.915241",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

pages = "267--272",

booktitle = "Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001",

address = "美國",

note = "2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 ; Conference date: 26-03-2001 Through 28-03-2001",

}

Ker, M-D, Lo, WY, Chen, TY, Tang, H, Chen, SS & Wang, MC 2001, Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process. in Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001., 915241, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2001-January, IEEE Computer Society, pp. 267-272, 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001, San Jose, United States, 26/03/01. https://doi.org/10.1109/ISQED.2001.915241

Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process. / Ker, Ming-Dou; Lo, Wen Yu; Chen, Tung Yang et al.
Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, 2001. p. 267-272 915241 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process

AU - Ker, Ming-Dou

AU - Lo, Wen Yu

AU - Chen, Tung Yang

AU - Tang, Howard

AU - Chen, S. S.

AU - Wang, M. C.

PY - 2001/3/28

Y1 - 2001/3/28

N2 - An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-μim shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.

AB - An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-μim shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.

UR - http://www.scopus.com/inward/record.url?scp=0009556831&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2001.915241

DO - 10.1109/ISQED.2001.915241

M3 - Conference contribution

AN - SCOPUS:0009556831

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 267

EP - 272

BT - Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001

PB - IEEE Computer Society

T2 - 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001

Y2 - 26 March 2001 through 28 March 2001

ER -

Ker MD, Lo WY, Chen TY, Tang H, Chen SS, Wang MC. Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society. 2001. p. 267-272. 915241. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2001.915241

Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this