Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Li Wei Chu; Chun Yu Lin; Shiang Yu Tsai; Ming-Dou Ker; Ming Hsiang Song; Chewn Pu Jou; Tse Hua Lu; Jen Chou Tseng; Ming Hsien Tsai; Tsun Lai Hsu; Ping Fang Hung; Tzu Heng Chang

doi:10.1109/ISCAS.2012.6271706

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Li Wei Chu^*, Chun Yu Lin, Shiang Yu Tsai, Ming-Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Tzu Heng Chang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

Original language	English
Pages	2127-2130
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271706
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

Keywords

Electrostatic discharge (ESD)
V band
radio frequency (RF)

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10.1109/ISCAS.2012.6271706

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Chu, L. W., Lin, C. Y., Tsai, S. Y., Ker, M.-D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F., & Chang, T. H. (2012). Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. 2127-2130. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271706

@conference{825c37b1d94946fda56e833eb1d81626,

title = "Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology",

abstract = "Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.",

keywords = "Electrostatic discharge (ESD), V band, radio frequency (RF)",

author = "Chu, {Li Wei} and Lin, {Chun Yu} and Tsai, {Shiang Yu} and Ming-Dou Ker and Song, {Ming Hsiang} and Jou, {Chewn Pu} and Lu, {Tse Hua} and Tseng, {Jen Chou} and Tsai, {Ming Hsien} and Hsu, {Tsun Lai} and Hung, {Ping Fang} and Chang, {Tzu Heng}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271706",

language = "English",

pages = "2127--2130",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

Chu, LW, Lin, CY, Tsai, SY, Ker, M-D, Song, MH, Jou, CP, Lu, TH, Tseng, JC, Tsai, MH, Hsu, TL, Hung, PF & Chang, TH 2012, 'Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology', Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/05/12 - 23/05/12 pp. 2127-2130. https://doi.org/10.1109/ISCAS.2012.6271706

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AU - Chu, Li Wei

AU - Lin, Chun Yu

AU - Tsai, Shiang Yu

AU - Ker, Ming-Dou

AU - Song, Ming Hsiang

AU - Jou, Chewn Pu

AU - Lu, Tse Hua

AU - Tseng, Jen Chou

AU - Tsai, Ming Hsien

AU - Hsu, Tsun Lai

AU - Hung, Ping Fang

AU - Chang, Tzu Heng

PY - 2012

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N2 - Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

AB - Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

KW - Electrostatic discharge (ESD)

KW - V band

KW - radio frequency (RF)

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

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ER -

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

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