@inproceedings{d61a0c1ffa0546f4a7a2011487442f54,
title = "Common-centroid FinFET placement considering the impact of gate misalignment",
abstract = "The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process variation based on the FinFET technology becomes even severer compared with the conventional planar CMOS technology. Such misalignment may increase the threshold voltage and decrease the drain current of a single transistor. When applying the FinFET technology to analog circuit design, the variation of drain currents will destroy the current matching among transistors and degrade the circuit performance. In this paper, we present the first FinFET placement technique for analog circuits considering the impact of gate misalignment together with systematic and random mismatch. Experimental results show that the proposed algorithms can obtain an optimized common-centroid FinFET placement with much better current matching.",
keywords = "Analog placement, Common centroid, FinFET, Gate misalignment",
author = "Wu, {Po Hsun} and Po-Hung Lin and X. Li and Ho, {Tsung Yi}",
year = "2015",
month = mar,
day = "29",
doi = "10.1145/2717764.2717769",
language = "English",
series = "Proceedings of the International Symposium on Physical Design",
publisher = "Association for Computing Machinery",
pages = "25--31",
booktitle = "ISPD 2015 - Proceedings of the ACM International Symposium on Physical Design 2015",
note = "18th ACM International Symposium on Physical Design, ISPD 2015 ; Conference date: 29-03-2015 Through 01-04-2015",
}