CMOS-RRAM based In-Memory Hamming Distance Calculation Technique

Manoj Kumar*, Ming Hung Wu, Tuo Hung Hou, Manan Suri*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We designed a CMOS-RRAM based in-memory Hamming Distance (HD) calculation technique providing additional degree of mismatch as compared to Content Addressable Memories (CAMs). One 2T2R (2-Transistor, 2-RRAM) cell is considered to store a single encoded bit of ternary information, while both the RRAM cells are programmed to complementary resistance states. The net current flowing through the 2T2R unit cell results in the HD. Moreover, the HD for various possible combinations of 16-bit input and stored data was shown through array level circuit simulations with integrated Transimpedence Amplifiers (TIAs) to convert row-wise accumulated current into output voltage. The 2T2R-based technique exhibits minimum 3× area and geq 3.6× power saving as compared to existing CMOSNVM (Non-Volatile Memory) counterparts.

Original languageEnglish
Title of host publicationIEEE Electron Devices Technology and Manufacturing Conference
Subtitle of host publicationStrengthening the Globalization in Semiconductors, EDTM 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350371529
DOIs
StatePublished - 2024
Event8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024 - Bangalore, India
Duration: 3 Mar 20246 Mar 2024

Publication series

NameIEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024

Conference

Conference8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024
Country/TerritoryIndia
CityBangalore
Period3/03/246/03/24

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