CMOS power amplifier with ESD protection design merged in matching network

Yu D. Shiu*, Bo Shih Huang, Ming-Dou Ker

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations

    Abstract

    A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-μm CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.

    Original languageEnglish
    Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
    Pages825-828
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2007
    Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
    Duration: 11 Dec 200714 Dec 2007

    Publication series

    NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

    Conference

    Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
    Country/TerritoryMorocco
    CityMarrakech
    Period11/12/0714/12/07

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