CMOS on-chip ESD protection design with substrate-triggering technique

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu

doi:10.1109/ICECS.1998.813319

CMOS on-chip ESD protection design with substrate-triggering technique

Ming-Dou Ker^*, Tung Yang Chen, Chung-Yu Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

Original language	English
Pages	273-276
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.1998.813319
State	Published - 1 Dec 1998
Event	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal Duration: 7 Sep 1998 → 10 Sep 1998

Conference

Conference	Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
City	Lisboa, Portugal
Period	7/09/98 → 10/09/98

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10.1109/ICECS.1998.813319

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title = "CMOS on-chip ESD protection design with substrate-triggering technique",

abstract = "To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu",

year = "1998",

month = dec,

day = "1",

doi = "10.1109/ICECS.1998.813319",

language = "English",

pages = "273--276",

note = "Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology ; Conference date: 07-09-1998 Through 10-09-1998",

}

Ker, M-D, Chen, TY & Wu, C-Y 1998, 'CMOS on-chip ESD protection design with substrate-triggering technique', Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal, 7/09/98 - 10/09/98 pp. 273-276. https://doi.org/10.1109/ICECS.1998.813319

CMOS on-chip ESD protection design with substrate-triggering technique. / Ker, Ming-Dou; Chen, Tung Yang; Wu, Chung-Yu.
1998. 273-276 Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal.

Research output: Contribution to conference › Paper › peer-review

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AU - Chen, Tung Yang

AU - Wu, Chung-Yu

PY - 1998/12/1

Y1 - 1998/12/1

N2 - To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

AB - To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

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Y2 - 7 September 1998 through 10 September 1998

ER -

CMOS on-chip ESD protection design with substrate-triggering technique

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