CMOS-compatible fabrication of room-temperature Ge QD single hole transistors

I. H. Chen; K. H. Chen; H. H. Chou; Pei-Wen Li

doi:10.1109/SNW.2010.5562548

CMOS-compatible fabrication of room-temperature Ge QD single hole transistors

I. H. Chen, K. H. Chen, H. H. Chou, Pei-Wen Li

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Precise control on quantum dot (QD) number and tunnel path in a self-organized manner is crucial for effective single electron tunneling. We experimentally demonstrated a single Ge QD (∼10 nm) self-aligned with nickel-silicide electrodes via Si₃N₄/SiO₂ tunnel barriers by thermally oxidizing a SiGe nanorod. The fabricated Ge QD single hole transistor (SHT) features with clear differential conductance and Coulomb-blockade oscillation behaviors at near room temperature.

Original language	English
Title of host publication	2010 Silicon Nanoelectronics Workshop, SNW 2010
DOIs	https://doi.org/10.1109/SNW.2010.5562548
State	Published - 22 Oct 2010
Event	2010 15th Silicon Nanoelectronics Workshop, SNW 2010 - Honolulu, HI, United States Duration: 13 Jun 2010 → 14 Jun 2010

Publication series

Name	2010 Silicon Nanoelectronics Workshop, SNW 2010

Conference

Conference	2010 15th Silicon Nanoelectronics Workshop, SNW 2010
Country/Territory	United States
City	Honolulu, HI
Period	13/06/10 → 14/06/10

Access to Document

10.1109/SNW.2010.5562548

Cite this

@inproceedings{16d7b0d2a512476db5a464e729acf515,

title = "CMOS-compatible fabrication of room-temperature Ge QD single hole transistors",

abstract = "Precise control on quantum dot (QD) number and tunnel path in a self-organized manner is crucial for effective single electron tunneling. We experimentally demonstrated a single Ge QD (∼10 nm) self-aligned with nickel-silicide electrodes via Si3N4/SiO2 tunnel barriers by thermally oxidizing a SiGe nanorod. The fabricated Ge QD single hole transistor (SHT) features with clear differential conductance and Coulomb-blockade oscillation behaviors at near room temperature.",

author = "Chen, {I. H.} and Chen, {K. H.} and Chou, {H. H.} and Pei-Wen Li",

year = "2010",

month = oct,

day = "22",

doi = "10.1109/SNW.2010.5562548",

language = "English",

isbn = "9781424477272",

series = "2010 Silicon Nanoelectronics Workshop, SNW 2010",

booktitle = "2010 Silicon Nanoelectronics Workshop, SNW 2010",

note = "2010 15th Silicon Nanoelectronics Workshop, SNW 2010 ; Conference date: 13-06-2010 Through 14-06-2010",

}

TY - GEN

T1 - CMOS-compatible fabrication of room-temperature Ge QD single hole transistors

AU - Chen, I. H.

AU - Chen, K. H.

AU - Chou, H. H.

AU - Li, Pei-Wen

PY - 2010/10/22

Y1 - 2010/10/22

N2 - Precise control on quantum dot (QD) number and tunnel path in a self-organized manner is crucial for effective single electron tunneling. We experimentally demonstrated a single Ge QD (∼10 nm) self-aligned with nickel-silicide electrodes via Si3N4/SiO2 tunnel barriers by thermally oxidizing a SiGe nanorod. The fabricated Ge QD single hole transistor (SHT) features with clear differential conductance and Coulomb-blockade oscillation behaviors at near room temperature.

AB - Precise control on quantum dot (QD) number and tunnel path in a self-organized manner is crucial for effective single electron tunneling. We experimentally demonstrated a single Ge QD (∼10 nm) self-aligned with nickel-silicide electrodes via Si3N4/SiO2 tunnel barriers by thermally oxidizing a SiGe nanorod. The fabricated Ge QD single hole transistor (SHT) features with clear differential conductance and Coulomb-blockade oscillation behaviors at near room temperature.

UR - http://www.scopus.com/inward/record.url?scp=77957989883&partnerID=8YFLogxK

U2 - 10.1109/SNW.2010.5562548

DO - 10.1109/SNW.2010.5562548

M3 - Conference contribution

AN - SCOPUS:77957989883

SN - 9781424477272

T3 - 2010 Silicon Nanoelectronics Workshop, SNW 2010

BT - 2010 Silicon Nanoelectronics Workshop, SNW 2010

T2 - 2010 15th Silicon Nanoelectronics Workshop, SNW 2010

Y2 - 13 June 2010 through 14 June 2010

ER -

CMOS-compatible fabrication of room-temperature Ge QD single hole transistors

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this