Clock and data recovery for optical links

This chapter focuses on the design of energy -efficient CDR circuits for highspeed optical links. In the first part, a BMCDR is introduced [3]. It incorporates a selective gating ring oscillator in a phase -locked loop (PLL). The selective gating oscillator is running at 1/n data rate, which enables high-speed operation with low power consumption. Meanwhile, the proposed BMCDR manifests both the advantages of instant phase locking and data jitter suppression in contrast to conventional gating -only or PLL-only CDRs. In the second part, a fully integrated optical receiver consisting of an integrating -type receiver front-end and a new baud -rate CDR is described [4]. A hybrid loop fi lter is proposed to facilitate programmable bandwidth with a constant phase margin. Both the experimental prototypes have small form factors and high energy efficiency. They demonstrate strong potentials to be applied in consumer electronics and high-performance computing platforms.