TY - GEN
T1 - Circuit performance of double-gate SOI CMOS
AU - Lin, C. H.
AU - Su, Pin
AU - Taur, Y.
AU - Xi, X.
AU - He, I.
AU - Niknejad, A. M.
AU - Chan, M.
AU - Hu, Chen-Ming
PY - 2003
Y1 - 2003
N2 - As CMOS technology is fast moving toward the scaling limit, the double-gate (DG) MOSFETs is considered the most promising structure to suppress the short channel effect for a given equivalent gate oxide thickness by using two gates to control the channel [1]. There are two main types of DG MOSFETs: ( 1 ) the symmetric DG (SDG) device with both gates of identical work functions, and (2) the asymmetric'DG (ADG) device with different work functions for the gates. Although the characteristics of SDG and ADG device have been investigated by many groups (2-4), the relative circuit performance of these two devices still remains controversial. In this paper, the performance of DG MOSFETs from the circuit-design perspective is examined via simulation using device structures based on the ITRS specification [ 5 ] . The propagation delay (l,J and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C,1ml) between two stages (Fig. 1).
AB - As CMOS technology is fast moving toward the scaling limit, the double-gate (DG) MOSFETs is considered the most promising structure to suppress the short channel effect for a given equivalent gate oxide thickness by using two gates to control the channel [1]. There are two main types of DG MOSFETs: ( 1 ) the symmetric DG (SDG) device with both gates of identical work functions, and (2) the asymmetric'DG (ADG) device with different work functions for the gates. Although the characteristics of SDG and ADG device have been investigated by many groups (2-4), the relative circuit performance of these two devices still remains controversial. In this paper, the performance of DG MOSFETs from the circuit-design perspective is examined via simulation using device structures based on the ITRS specification [ 5 ] . The propagation delay (l,J and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C,1ml) between two stages (Fig. 1).
UR - http://www.scopus.com/inward/record.url?scp=84945281663&partnerID=8YFLogxK
U2 - 10.1109/ISDRS.2003.1272091
DO - 10.1109/ISDRS.2003.1272091
M3 - Conference contribution
AN - SCOPUS:84945281663
T3 - 2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
SP - 266
EP - 267
BT - 2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Semiconductor Device Research Symposium, ISDRS 2003
Y2 - 10 December 2003 through 12 December 2003
ER -