@inproceedings{67ef56f3547c4d5886ab7e52b0c4aec8,
title = "Circuit performance analysis of negative capacitance FinFETs",
abstract = "Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.",
author = "S. Khandelwal and Khan, {A. I.} and Duarte, {J. P.} and Sachid, {A. B.} and S. Salahuddin and Chen-Ming Hu",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",
year = "2016",
month = sep,
day = "21",
doi = "10.1109/VLSIT.2016.7573446",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016",
address = "United States",
}