Circuit performance analysis of negative capacitance FinFETs

S. Khandelwal, A. I. Khan, J. P. Duarte, A. B. Sachid, S. Salahuddin, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

38 Scopus citations

Abstract

Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ∼10×. Optimization of the FE layer parameters can further boost the device performance.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006373
DOIs
StatePublished - 21 Sep 2016
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 13 Jun 201616 Jun 2016

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2016-September
ISSN (Print)0743-1562

Conference

Conference36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/TerritoryUnited States
CityHonolulu
Period13/06/1616/06/16

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