Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process

Wen Yi Chen; Ming-Dou Ker

doi:10.1109/TCSI.2010.2043986

Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process

Wen Yi Chen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-μm 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- μm 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.

Original language	English
Article number	5439899
Pages (from-to)	1039-1047
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	57
Issue number	5
DOIs	https://doi.org/10.1109/TCSI.2010.2043986
State	Published - 29 Mar 2010

Keywords

Bipolar-CMOS-DMOS (BCD) process
Body current injection
Electrostatic discharge (ESD)
Lateral double-diffused metal-oxide-semiconductor (LDMOS)

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10.1109/TCSI.2010.2043986

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title = "Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process",

abstract = "The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-μm 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- μm 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.",

keywords = "Bipolar-CMOS-DMOS (BCD) process, Body current injection, Electrostatic discharge (ESD), Lateral double-diffused metal-oxide-semiconductor (LDMOS)",

author = "Chen, {Wen Yi} and Ming-Dou Ker",

year = "2010",

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doi = "10.1109/TCSI.2010.2043986",

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TY - JOUR

T1 - Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process

AU - Chen, Wen Yi

AU - Ker, Ming-Dou

PY - 2010/3/29

Y1 - 2010/3/29

N2 - The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-μm 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- μm 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.

AB - The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-μm 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- μm 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.

KW - Bipolar-CMOS-DMOS (BCD) process

KW - Body current injection

KW - Electrostatic discharge (ESD)

KW - Lateral double-diffused metal-oxide-semiconductor (LDMOS)

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Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process

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Keywords

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