Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process

Wen Yi Chen*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    16 Scopus citations

    Abstract

    The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-μm 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- μm 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.

    Original languageEnglish
    Article number5439899
    Pages (from-to)1039-1047
    Number of pages9
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Volume57
    Issue number5
    DOIs
    StatePublished - 2010

    Keywords

    • Bipolar-CMOS-DMOS (BCD) process
    • Body current injection
    • Electrostatic discharge (ESD)
    • Lateral double-diffused metal-oxide-semiconductor (LDMOS)

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