Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration

Hong Wen Chiou, Jia Hao Jiang, Yu Teng Chang, Yu Min Lee, Chi Wen Pan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning techniques, the developed placer can find the solution fast with the optimized total wirelength (TWL) on half-perimeter wirelength (HPWL). Additionally, with the post placement procedure, the placer reduces maximum temperatures with slight increase of wirelength. Experimental results show that the placer can not only find better optimized TWL (reducing 1.035% HPWL) but also speed up at most two orders of magnitude than the prior art. With thermal consideration, the placer can reduce the maximum temperature up to 8.214 °C with an average 5.376% increase of TWL.

Original languageEnglish
Title of host publicationASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages7-12
Number of pages6
ISBN (Electronic)9781450397834
DOIs
StatePublished - 16 Jan 2023
Event28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023 - Tokyo, Japan
Duration: 16 Jan 202319 Jan 2023

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023
Country/TerritoryJapan
CityTokyo
Period16/01/2319/01/23

Keywords

  • 2.5D IC
  • chiplet placement
  • sequence pair
  • thermal

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