Chip design of A 32-b logarithmic number system

Sheng-Chieh Huang*, Liang Gee Chen, Thou Ho Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations


To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

Original languageEnglish
Pages (from-to)167-170
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 30 May 19942 Jun 1994

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