Chip design of A 32-b logarithmic number system

Sheng-Chieh Huang; Liang Gee Chen; Thou Ho Chen

doi:10.1109/ISCAS.1994.409224

Chip design of A 32-b logarithmic number system

Sheng-Chieh Huang^*, Liang Gee Chen, Thou Ho Chen

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log₂(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2^0.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

Original language	English
Pages (from-to)	167-170
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
DOIs	https://doi.org/10.1109/ISCAS.1994.409224
State	Published - 1 Dec 1994
Event	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: 30 May 1994 → 2 Jun 1994

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10.1109/ISCAS.1994.409224

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title = "Chip design of A 32-b logarithmic number system",

abstract = "To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.",

author = "Sheng-Chieh Huang and Chen, {Liang Gee} and Chen, {Thou Ho}",

year = "1994",

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AU - Huang, Sheng-Chieh

AU - Chen, Liang Gee

AU - Chen, Thou Ho

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Y1 - 1994/12/1

N2 - To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

AB - To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

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U2 - 10.1109/ISCAS.1994.409224

DO - 10.1109/ISCAS.1994.409224

M3 - Conference article

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SN - 0271-4310

VL - 4

SP - 167

EP - 170

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)

Y2 - 30 May 1994 through 2 June 1994

ER -

Chip design of A 32-b logarithmic number system

Abstract

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