Characterization on ESD devices with test structures in silicon Germanium RF BiCMOS process

Ming-Dou Ker; Woei Lin Wu; Chyh Yih Chang

doi:10.1109/ICMTS.2004.1309292

Characterization on ESD devices with test structures in silicon Germanium RF BiCMOS process

Ming-Dou Ker^*, Woei Lin Wu, Chyh Yih Chang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Different electrostatic discharge (ESD) devices in a 0.35-μm silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip BSD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), Hgh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.

Original language	English
Pages	7-12
Number of pages	6
DOIs	https://doi.org/10.1109/ICMTS.2004.1309292
State	Published - Mar 2004
Event	Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004) - Awaji, Japan Duration: 22 Mar 2004 → 25 Mar 2004

Conference

Conference	Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004)
Country/Territory	Japan
City	Awaji
Period	22/03/04 → 25/03/04

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10.1109/ICMTS.2004.1309292

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title = "Characterization on ESD devices with test structures in silicon Germanium RF BiCMOS process",

abstract = "Different electrostatic discharge (ESD) devices in a 0.35-μm silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip BSD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), Hgh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.",

author = "Ming-Dou Ker and Wu, {Woei Lin} and Chang, {Chyh Yih}",

year = "2004",

month = mar,

doi = "10.1109/ICMTS.2004.1309292",

language = "English",

pages = "7--12",

note = "Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004) ; Conference date: 22-03-2004 Through 25-03-2004",

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AU - Ker, Ming-Dou

AU - Wu, Woei Lin

AU - Chang, Chyh Yih

PY - 2004/3

Y1 - 2004/3

N2 - Different electrostatic discharge (ESD) devices in a 0.35-μm silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip BSD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), Hgh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.

AB - Different electrostatic discharge (ESD) devices in a 0.35-μm silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip BSD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), Hgh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.

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U2 - 10.1109/ICMTS.2004.1309292

DO - 10.1109/ICMTS.2004.1309292

M3 - Paper

AN - SCOPUS:3042613316

SP - 7

EP - 12

T2 - Proceedings of the 2004 International Conference on Microelectronic Test Structures (ICMTS 2004)

Y2 - 22 March 2004 through 25 March 2004

ER -

Characterization on ESD devices with test structures in silicon Germanium RF BiCMOS process

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