Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

Shih Ching Chen, Ting Chang Chang*, Po-Tsun Liu, Yung Chun Wu, Po Shun Lin, Shih Cheng Chen, Jing Yi Chin, S. M. Sze, Chun-Yen Chang, Chen Hsin Lien

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The Vth decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming Vth shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing Vth shift is improved from - 0.3 V to - 1.3 V at - 14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 °C and a 0.8 V memory window after 5 × 103 P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display.

Original languageEnglish
Pages (from-to)1287-1291
Number of pages5
JournalSurface and Coatings Technology
Issue number4-7
StatePublished - 15 Dec 2007


  • Nanowire
  • Nonvolatile memory
  • Poly-Si
  • Thin film transistor (TFT)


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