Characteristics of gate-all-around silicon nanowire and nanosheet MOSFETs with various spacers

Sekhar Reddy Kola, Yiming Li-*, Narasimhulu Thoti

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔID/ID×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.

Original languageEnglish
Title of host publication2020 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages79-82
Number of pages4
ISBN (Electronic)9784863487635
DOIs
StatePublished - 23 Sep 2020
Event2020 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2020 - Virtual, Kobe, Japan
Duration: 3 Sep 20206 Oct 2020

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2020-September

Conference

Conference2020 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2020
Country/TerritoryJapan
CityVirtual, Kobe
Period3/09/206/10/20

Keywords

  • DC characteristics
  • Gate-all-around
  • MOSFETs.
  • Nanowire
  • Nonosheet
  • RTN
  • SCT

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