Abstract
A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high Ion Ioff current ratio of 7 × 10-8 (VG = 4 V and VD = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.
Original language | English |
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Article number | 7118129 |
Pages (from-to) | 405-409 |
Number of pages | 5 |
Journal | IEEE Journal of the Electron Devices Society |
Volume | 3 |
Issue number | 5 |
DOIs | |
State | Published - 1 Sep 2015 |
Keywords
- Gate-all-around (GAA)
- junctionless (JL)
- nanowire (NW)
- poly-Si
- sidewall spacer
- transistor