Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

You Tai Chang, Ruei Jen Wu, Kang Ping Peng, Chun Jung Su, Pei-Wen Li, Horng-Chih Lin*

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

    Original languageEnglish
    Title of host publication2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages57-58
    Number of pages2
    ISBN (Electronic)9781728197357
    ISBN (Print)978-1-7281-9736-4
    DOIs
    StatePublished - Jun 2020
    Event2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
    Duration: 13 Jun 202014 Jun 2020

    Publication series

    Name2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

    Conference

    Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
    Country/TerritoryUnited States
    CityHonolulu
    Period13/06/2014/06/20

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