Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

You Tai Chang; Ruei Jen Wu; Kang Ping Peng; Chun Jung Su; Pei-Wen Li; Horng-Chih Lin

doi:10.1109/SNW50361.2020.9131654

Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

You Tai Chang, Ruei Jen Wu, Kang Ping Peng, Chun Jung Su, Pei-Wen Li, Horng-Chih Lin^*

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

Original language	English
Title of host publication	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	57-58
Number of pages	2
ISBN (Electronic)	9781728197357
ISBN (Print)	978-1-7281-9736-4
DOIs	https://doi.org/10.1109/SNW50361.2020.9131654
State	Published - Jun 2020
Event	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States Duration: 13 Jun 2020 → 14 Jun 2020

Publication series

Name	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Country/Territory	United States
City	Honolulu
Period	13/06/20 → 14/06/20

Access to Document

10.1109/SNW50361.2020.9131654

Cite this

Chang, Y. T., Wu, R. J., Peng, K. P., Su, C. J., Li, P.-W., & Lin, H.-C. (2020). Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets. In 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 (pp. 57-58). Article 9131654 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW50361.2020.9131654

@inproceedings{96438b288a474549b15e802b21e957b7,

title = "Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets",

abstract = "In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.",

author = "Chang, {You Tai} and Wu, {Ruei Jen} and Peng, {Kang Ping} and Su, {Chun Jung} and Pei-Wen Li and Horng-Chih Lin",

year = "2020",

month = jun,

doi = "10.1109/SNW50361.2020.9131654",

language = "English",

isbn = "978-1-7281-9736-4",

series = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "57--58",

booktitle = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",

address = "美國",

note = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 ; Conference date: 13-06-2020 Through 14-06-2020",

}

Chang, YT, Wu, RJ, Peng, KP, Su, CJ, Li, P-W & Lin, H-C 2020, Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets. in 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020., 9131654, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Institute of Electrical and Electronics Engineers Inc., pp. 57-58, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Honolulu, United States, 13/06/20. https://doi.org/10.1109/SNW50361.2020.9131654

Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets. / Chang, You Tai; Wu, Ruei Jen; Peng, Kang Ping et al.
2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 57-58 9131654 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chang, You Tai

AU - Wu, Ruei Jen

AU - Peng, Kang Ping

AU - Su, Chun Jung

AU - Li, Pei-Wen

AU - Lin, Horng-Chih

PY - 2020/6

Y1 - 2020/6

N2 - In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

AB - In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

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DO - 10.1109/SNW50361.2020.9131654

M3 - Conference contribution

AN - SCOPUS:85092128284

SN - 978-1-7281-9736-4

T3 - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

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BT - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

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ER -

Chang YT, Wu RJ, Peng KP, Su CJ, Li PW , Lin HC. Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets. In 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 57-58. 9131654. (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020). doi: 10.1109/SNW50361.2020.9131654

Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

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