Characteristic optimization of single- and double-gate tunneling field effect transistors

Kuo Fu Lee; Yiming Li; Chun Yen Yiu; Zhong Cheng Su; I. Shiu Lo; Hui Wen Cheng; Ming Hung Han; Thet Thet Khaing

Characteristic optimization of single- and double-gate tunneling field effect transistors

Kuo Fu Lee^*, Yiming Li, Chun Yen Yiu, Zhong Cheng Su, I. Shiu Lo, Hui Wen Cheng, Ming Hung Han, Thet Thet Khaing

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (ID). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 10²² cm³, and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (I_on/I_off) of 5×10 ⁹ are obtained, compared with the single-gate device.

Original language	English
Title of host publication	Nanotechnology 2010
Subtitle of host publication	Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Pages	65-68
Number of pages	4
State	Published - Jan 2010
Event	Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 - Anaheim, CA, United States Duration: 21 Jun 2010 → 24 Jun 2010

Publication series

Name	Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Volume	2

Conference

Conference	Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Country/Territory	United States
City	Anaheim, CA
Period	21/06/10 → 24/06/10

Keywords

DC characteristic
Device simulation
Field Effect Transistor
On/off state current ratio
Optimal parameters
Subthreshold slop
Tunneling

Cite this

Lee, K. F., Li, Y., Yiu, C. Y., Su, Z. C., Lo, I. S., Cheng, H. W., Han, M. H., & Khaing, T. T. (2010). Characteristic optimization of single- and double-gate tunneling field effect transistors. In Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 (pp. 65-68). (Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010; Vol. 2).

Lee, Kuo Fu ; Li, Yiming ; Yiu, Chun Yen et al. / Characteristic optimization of single- and double-gate tunneling field effect transistors. Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010. 2010. pp. 65-68 (Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010).

@inproceedings{25e7c5d56ef9448ea94ea85d0370c5bf,

title = "Characteristic optimization of single- and double-gate tunneling field effect transistors",

abstract = "Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (ID). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 1022 cm3, and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (Ion/Ioff) of 5×10 9 are obtained, compared with the single-gate device.",

keywords = "DC characteristic, Device simulation, Field Effect Transistor, On/off state current ratio, Optimal parameters, Subthreshold slop, Tunneling",

author = "Lee, {Kuo Fu} and Yiming Li and Yiu, {Chun Yen} and Su, {Zhong Cheng} and Lo, {I. Shiu} and Cheng, {Hui Wen} and Han, {Ming Hung} and Khaing, {Thet Thet}",

year = "2010",

month = jan,

language = "English",

isbn = "9781439834022",

series = "Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010",

pages = "65--68",

booktitle = "Nanotechnology 2010",

note = "Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 ; Conference date: 21-06-2010 Through 24-06-2010",

}

Lee, KF, Li, Y, Yiu, CY, Su, ZC, Lo, IS, Cheng, HW, Han, MH & Khaing, TT 2010, Characteristic optimization of single- and double-gate tunneling field effect transistors. in Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010. Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010, vol. 2, pp. 65-68, Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010, Anaheim, CA, United States, 21/06/10.

Characteristic optimization of single- and double-gate tunneling field effect transistors. / Lee, Kuo Fu; Li, Yiming; Yiu, Chun Yen et al.
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010. 2010. p. 65-68 (Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Characteristic optimization of single- and double-gate tunneling field effect transistors

AU - Lee, Kuo Fu

AU - Li, Yiming

AU - Yiu, Chun Yen

AU - Su, Zhong Cheng

AU - Lo, I. Shiu

AU - Cheng, Hui Wen

AU - Han, Ming Hung

AU - Khaing, Thet Thet

PY - 2010/1

Y1 - 2010/1

N2 - Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (ID). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 1022 cm3, and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (Ion/Ioff) of 5×10 9 are obtained, compared with the single-gate device.

AB - Optimal single- and double-gate tunneling field-effect transistor (TFET) with a structure of p++ source, intrinsic channel and n+ drain region are explored. Two-dimensional device simulation is adopted to assess device characteristic influenced by the source doping, the channel doping and the thickness of junction overlap between the source and gate. The result of this study shows that the source doping and junction overlap significantly affect the drain current (ID). Then, we compare the single- and double-gate TFETs with the optimized parameters, where the junction overlap is 6 nm, the source doping is 1022 cm3, and the intrinsic channel doping. For the explored double-gate TFET, a steeper subthreshold slope (SS) of 32 mV/dec and a higher on/off current ratio (Ion/Ioff) of 5×10 9 are obtained, compared with the single-gate device.

KW - DC characteristic

KW - Device simulation

KW - Field Effect Transistor

KW - On/off state current ratio

KW - Optimal parameters

KW - Subthreshold slop

KW - Tunneling

UR - http://www.scopus.com/inward/record.url?scp=78049432889&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:78049432889

SN - 9781439834022

T3 - Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010

SP - 65

EP - 68

BT - Nanotechnology 2010

T2 - Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010

Y2 - 21 June 2010 through 24 June 2010

ER -

Lee KF, Li Y, Yiu CY, Su ZC, Lo IS, Cheng HW et al. Characteristic optimization of single- and double-gate tunneling field effect transistors. In Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010. 2010. p. 65-68. (Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010).

Characteristic optimization of single- and double-gate tunneling field effect transistors

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