Challenges and designs of TFET for digital applications

Ming Long Fan, Yin Nien Chen, Pin Su*, Ching Te Chuang

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

    4 Scopus citations


    This chapter reviews the challenges and designs of digital TFET circuits. Several fundamental features of TFET such as unidirectional conduction, delayed saturation, and enhanced Miller capacitance are described with emphasis on their impacts on the functionality and robustness of logic and SRAM circuits. For TFET logic circuits, structural innovations and device design are demonstrated to facilitate compact circuit design and performance improvement. For SRAM, the advantages of hybrid TFET-MOSFET 8T SRAM cell in stability and efficiency of WRITE-assisted circuit to enhance performance are addressed. Moreover, the variability and backgate bias technique for TFET digital circuit design are highlighted.

    Original languageEnglish
    Title of host publicationTunneling Field Effect Transistor Technology
    PublisherSpringer International Publishing
    Number of pages22
    ISBN (Electronic)9783319316536
    ISBN (Print)9783319316512
    StatePublished - 1 Jan 2016


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