CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin; Ming-Dou Ker

doi:10.1109/IPFA.2010.5532223

CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

Original language	English
Title of host publication	IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs	https://doi.org/10.1109/IPFA.2010.5532223
State	Published - 15 Sep 2010
Event	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, Singapore Duration: 5 Jul 2010 → 9 Jul 2010

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
Country/Territory	Singapore
City	Singapore
Period	5/07/10 → 9/07/10

Access to Document

10.1109/IPFA.2010.5532223

Cite this

Lin, C. Y., & Ker, M-D. (2010). CDM ESD protection design with initial-on concept in nanoscale CMOS process. In IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits [5532223] (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2010.5532223

@inproceedings{fc1dbb94c68b447fbdcdc394dc1052b1,

title = "CDM ESD protection design with initial-on concept in nanoscale CMOS process",

abstract = "Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.",

author = "Lin, {Chun Yu} and Ming-Dou Ker",

year = "2010",

month = sep,

day = "15",

doi = "10.1109/IPFA.2010.5532223",

language = "English",

isbn = "9781424455973",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits",

note = "17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 ; Conference date: 05-07-2010 Through 09-07-2010",

}

Lin, CY & Ker, M-D 2010, CDM ESD protection design with initial-on concept in nanoscale CMOS process. in IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits., 5532223, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010, Singapore, Singapore, 5/07/10. https://doi.org/10.1109/IPFA.2010.5532223

CDM ESD protection design with initial-on concept in nanoscale CMOS process. / Lin, Chun Yu; Ker, Ming-Dou.
IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits. 2010. 5532223 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - CDM ESD protection design with initial-on concept in nanoscale CMOS process

AU - Lin, Chun Yu

AU - Ker, Ming-Dou

PY - 2010/9/15

Y1 - 2010/9/15

N2 - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

AB - Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

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U2 - 10.1109/IPFA.2010.5532223

DO - 10.1109/IPFA.2010.5532223

M3 - Conference contribution

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SN - 9781424455973

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

BT - IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits

T2 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010

Y2 - 5 July 2010 through 9 July 2010

ER -

CDM ESD protection design with initial-on concept in nanoscale CMOS process

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