Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example

Jen Chieh Liu, Chung Wei Hsu, I. Ting Wang, Tuo-Hung Hou*

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    14 Scopus citations


    This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.

    Original languageEnglish
    Article number7140778
    Pages (from-to)2510-2516
    Number of pages7
    JournalIEEE Transactions on Electron Devices
    Issue number8
    StatePublished - 1 Aug 2015


    • Multilevel-cell (MLC)
    • resistive random access memory (RRAM)
    • write scheme


    Dive into the research topics of 'Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example'. Together they form a unique fingerprint.

    Cite this