Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    36 Scopus citations

    Abstract

    The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.

    Original languageEnglish
    Article number5597958
    Pages (from-to)2476-2486
    Number of pages11
    JournalIEEE Journal of Solid-State Circuits
    Volume45
    Issue number11
    DOIs
    StatePublished - 1 Nov 2010

    Keywords

    • Big field-effect transistor (BigFET)
    • electrostatic discharge (ESD)
    • holding voltage
    • power-rail ESD clamp circuit

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