BSIM4 gate leakage model including source-drain partition

K. M. Cao; W. C. Lee; W. Liu; X. Jin; Pin Su; S. K.H. Fung; J. X. An; B. Yu; Chen-Ming Hu

doi:10.1109/IEDM.2000.904442

BSIM4 gate leakage model including source-drain partition

K. M. Cao^*, W. C. Lee, W. Liu, X. Jin, Pin Su, S. K.H. Fung, J. X. An, B. Yu, Chen-Ming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

169 Scopus citations

Abstract

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

Original language	English
Pages (from-to)	815-818
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2000.904442
State	Published - 2000
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 10 Dec 2000 → 13 Dec 2000

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title = "BSIM4 gate leakage model including source-drain partition",

abstract = "Gate dielectric leakage current becomes a serious concern as sub-20{\AA} gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.",

author = "Cao, {K. M.} and Lee, {W. C.} and W. Liu and X. Jin and Pin Su and Fung, {S. K.H.} and An, {J. X.} and B. Yu and Chen-Ming Hu",

year = "2000",

doi = "10.1109/IEDM.2000.904442",

language = "English",

pages = "815--818",

journal = "Technical Digest - International Electron Devices Meeting",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - JOUR

T1 - BSIM4 gate leakage model including source-drain partition

AU - Cao, K. M.

AU - Lee, W. C.

AU - Liu, W.

AU - Jin, X.

AU - Su, Pin

AU - Fung, S. K.H.

AU - An, J. X.

AU - Yu, B.

AU - Hu, Chen-Ming

PY - 2000

Y1 - 2000

N2 - Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

AB - Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed. This model has been implemented in BSIM4.

UR - http://www.scopus.com/inward/record.url?scp=0034453479&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2000.904442

DO - 10.1109/IEDM.2000.904442

M3 - Conference article

AN - SCOPUS:0034453479

SN - 0163-1918

SP - 815

EP - 818

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

BSIM4 gate leakage model including source-drain partition

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