Abstract
Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.
Original language | English |
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Title of host publication | 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479962754 |
DOIs | |
State | Published - 28 May 2015 |
Event | 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015 |
Publication series
Name | 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 |
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Conference
Conference | 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 |
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Country/Territory | Taiwan |
City | Hsinchu |
Period | 27/04/15 → 29/04/15 |
Keywords
- BRAM efficient
- FPGA
- multi-ported memory