BRAM efficient multi-ported memory on FPGA

Jiun Liang Lin; Bo-Cheng Lai

doi:10.1109/VLSI-DAT.2015.7114526

BRAM efficient multi-ported memory on FPGA

Jiun Liang Lin, Bo-Cheng Lai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114526
State	Published - 28 May 2015
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	27/04/15 → 29/04/15

Keywords

BRAM efficient
FPGA
multi-ported memory

Access to Document

10.1109/VLSI-DAT.2015.7114526

Cite this

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title = "BRAM efficient multi-ported memory on FPGA",

abstract = "Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.",

keywords = "BRAM efficient, FPGA, multi-ported memory",

author = "Lin, {Jiun Liang} and Bo-Cheng Lai",

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Lin, JL & Lai, B-C 2015, BRAM efficient multi-ported memory on FPGA. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114526, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114526

BRAM efficient multi-ported memory on FPGA. / Lin, Jiun Liang; Lai, Bo-Cheng.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114526 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.

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BRAM efficient multi-ported memory on FPGA

Abstract

Publication series

Conference

Keywords

Access to Document

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