Board level ESD of driver ICs on LCD panels

C. T. Hsu*, J. C. Tseng, Y. L. Chen, F. Y. Tsai, S. H. Yu, P. A. Chen, Ming-Dou Ker

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    1 Scopus citations


    A method utilizing Charged Device Model (CDM) discharging to emulate real-world Charged Board Model (CBM) discharging was proposed and successfully addressed the weakest spot of whole chip. In order to extract the correlation between CDM pre-fail voltage VCDM and CBM pre-fail voltage V CBM, the capacitance and discharging waveforms of output pin on an IC and Printed Circuit Board (PCB) were measured. The results showed that the CBM evaluation board (EB) was not a must for large-size chip, as LCD driver ICs. CDM discharging can be used to direct investigate the weak point of design/layout for large-size chip. Besides, this paper addresses the guidelines about chip-level ESD cell design and layout optimization against CBM ESD damage.

    Original languageEnglish
    Title of host publication2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
    Number of pages2
    StatePublished - 25 Sep 2007
    Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
    Duration: 15 Apr 200719 Apr 2007

    Publication series

    NameAnnual Proceedings - Reliability Physics (Symposium)
    ISSN (Print)0099-9512


    Conference45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
    Country/TerritoryUnited States
    CityPhoenix, AZ


    • CBM
    • CDM
    • ESD
    • HBM
    • PCB


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