Bias-Induced Instability of 4H-SiC CMOS

Keyphrases

• 4H-SiC 100%
• Annealing Process 50%
• Bias Stress 50%
• Circuit Application 50%
• Complementary Metal Oxide Semiconductor 100%
• Control Circuit 50%
• Electrical Characteristics 50%
• Electrical Stability 50%
• Hole Trapping 50%
• Interface Optimization 50%
• Metal-oxide-semiconductor Devices 50%
• Negative Bias Stress 50%
• NMOSFET 50%
• NO Annealing 50%
• PMOSFET 50%
• Positive Bias Stress 50%
• Positive Holes 50%
• Post-oxidation Annealing 50%
• Process Optimization 50%

Engineering

• Annealing Process 100%
• Complementary Metal-Oxide-Semiconductor 100%
• Complementary Metal-Oxide-Semiconductor Device 100%
• Electrical Stability 100%
• Test Result 100%