Bias-Induced Instability of 4H-SiC CMOS

Yu Xin Wen*, Bing Yue Tsui

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

1 Scopus citations

Abstract

4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N2-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

Original languageEnglish
Title of host publicationMaterials Science Forum
PublisherTrans Tech Publications Ltd.
Pages103-107
Number of pages5
DOIs
StatePublished - 2023

Publication series

NameMaterials Science Forum
Volume1092
ISSN (Print)0255-5476
ISSN (Electronic)1662-9752

Keywords

  • Bias temperature instability (BTI)
  • Post-oxidation annealing (POA)
  • Silicon carbide (SiC)

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