TY - GEN
T1 - Bias- and temperature-assisted trapping/de-trapping of RON degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate
AU - Zhang, Jin Ming
AU - Hsieh, Ting En
AU - Wu, Tian-Li
AU - Chen, Szu Hao
AU - Chen, Shi Xuan
AU - Chou, Po Chien
AU - Chang, Edward Yi
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/5
Y1 - 2017/10/5
N2 - In this study, we investigate the RON degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase RON degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the RON degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases further, the RON degradation is reduced. Third, the RON degradation slowly increases again. RON degradation is characterized with different temperatures, the results show that 1) high temperature leads to a smaller RON degradation compared to the result at room temperature and 2) high temperature shifts the peak of the RON degradation at a lower drain bias. A possible mechanism that the trapping and de-trapping could occur due to the high temperature and high drain bias is proposed to explain the observed results.
AB - In this study, we investigate the RON degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase RON degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the RON degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases further, the RON degradation is reduced. Third, the RON degradation slowly increases again. RON degradation is characterized with different temperatures, the results show that 1) high temperature leads to a smaller RON degradation compared to the result at room temperature and 2) high temperature shifts the peak of the RON degradation at a lower drain bias. A possible mechanism that the trapping and de-trapping could occur due to the high temperature and high drain bias is proposed to explain the observed results.
UR - http://www.scopus.com/inward/record.url?scp=85045044344&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2017.8060181
DO - 10.1109/IPFA.2017.8060181
M3 - Conference contribution
AN - SCOPUS:85045044344
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 1
EP - 4
BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Y2 - 4 July 2017 through 7 July 2017
ER -