Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process

Karuna Nidhi; Ming-Dou Ker; Jian Hsing Lee; Shao Chang Huang

doi:10.1109/TED.2019.2916032

Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process

Karuna Nidhi, Ming-Dou Ker^*, Jian Hsing Lee, Shao Chang Huang

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I_AV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.

Original language	English
Article number	8723307
Pages (from-to)	3040-3048
Number of pages	9
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	7
DOIs	https://doi.org/10.1109/TED.2019.2916032
State	Published - 1 Jul 2019

Keywords

Avalanche ruggedness
Avalanche safe-operating-area (A-SOA)
Current in avalanche (IAV)
Large-array device (LAD)
Time in avalanche (tAV)
Total gate charge (Qg)
Unclamped inductive switching (UIS)

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title = "Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process",

abstract = "Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.",

keywords = "Avalanche ruggedness, Avalanche safe-operating-area (A-SOA), Current in avalanche (IAV), Large-array device (LAD), Time in avalanche (tAV), Total gate charge (Qg), Unclamped inductive switching (UIS)",

author = "Karuna Nidhi and Ming-Dou Ker and Lee, {Jian Hsing} and Huang, {Shao Chang}",

year = "2019",

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AU - Nidhi, Karuna

AU - Ker, Ming-Dou

AU - Lee, Jian Hsing

AU - Huang, Shao Chang

PY - 2019/7/1

Y1 - 2019/7/1

N2 - Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.

AB - Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (IAV) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12μm.

KW - Avalanche ruggedness

KW - Avalanche safe-operating-area (A-SOA)

KW - Current in avalanche (IAV)

KW - Large-array device (LAD)

KW - Time in avalanche (tAV)

KW - Total gate charge (Qg)

KW - Unclamped inductive switching (UIS)

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ER -

Avalanche ruggedness capability and improvement of 5-v n-channel large-array mosfet in bcd process

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