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Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
- Ming-Dou Ker*
- , Hsin Chin Jiang
- , Jeng Jie Peng
- , Tzay Luen Shieh
*Corresponding author for this work
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
11
Scopus
citations