Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

Ming-Dou Ker; Hsin Chin Jiang; Jeng Jie Peng; Tzay Luen Shieh

doi:10.1109/ICECS.2001.957690

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

Ming-Dou Ker^*, Hsin Chin Jiang, Jeng Jie Peng, Tzay Luen Shieh

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	113-116
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2001.957690
State	Published - 1 Dec 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2 Sep 2001 → 5 Sep 2001

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Conference

Conference	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	2/09/01 → 5/09/01

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10.1109/ICECS.2001.957690

Cite this

Ker, M.-D., Jiang, H. C., Peng, J. J., & Shieh, T. L. (2001). Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems (pp. 113-116). Article 957690 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1). https://doi.org/10.1109/ICECS.2001.957690

@inproceedings{2c64ad60db35455ebb7eff85695f7a98,

title = "Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's",

abstract = "A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a {"}Guard Ring Automation{"} program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.",

author = "Ming-Dou Ker and Jiang, {Hsin Chin} and Peng, {Jeng Jie} and Shieh, {Tzay Luen}",

year = "2001",

month = dec,

day = "1",

doi = "10.1109/ICECS.2001.957690",

language = "English",

isbn = "0780370570",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "113--116",

booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",

note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",

}

Ker, M-D, Jiang, HC, Peng, JJ & Shieh, TL 2001, Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957690, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 113-116, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 2/09/01. https://doi.org/10.1109/ICECS.2001.957690

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. / Ker, Ming-Dou; Jiang, Hsin Chin; Peng, Jeng Jie et al.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 113-116 957690 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Peng, Jeng Jie

AU - Shieh, Tzay Luen

PY - 2001/12/1

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N2 - A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.

AB - A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.

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M3 - Conference contribution

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T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

Ker MD, Jiang HC, Peng JJ, Shieh TL. Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 113-116. 957690. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2001.957690

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

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